
module  float_add_sub_altbarrel_shift_35e
	( 
	aclr,
	clk_en,
	clock,
	data,
	distance,
	result) ;
	input   aclr;
	input   clk_en;
	input   clock;
	input   [25:0]  data;
	input   [4:0]  distance;
	output   [25:0]  result;

	reg	[25:0]	sbit_piper1d;
	reg	sel_pipec3r1d;
	reg	sel_pipec4r1d;
	wire	[25:0]	smux_w0;
	wire	[25:0]	smux_w1;
	wire	[25:0]	smux_w2;
	wire	[25:0]	smux_w3;
	wire	[25:0]	smux_w4;

	always @ ( posedge clock) begin
		sbit_piper1d <= smux_w2[25:0];
		sel_pipec3r1d <= distance[3];
		sel_pipec4r1d <= distance[4];
  end

  assign result  = sel_pipec4r1d ? {      smux_w3[25-16: 0], 16'b0} :      smux_w3[25:0];
  assign smux_w3 = sel_pipec3r1d ? { sbit_piper1d[25- 8: 0],  8'b0} : sbit_piper1d[25:0];
  assign smux_w2 =   distance[2] ? {      smux_w1[25- 4: 0],  4'b0} :      smux_w1[25:0];
  assign smux_w1 =   distance[1] ? {      smux_w0[25- 2: 0],  2'b0} :      smux_w0[25:0];
  assign smux_w0 =   distance[0] ? {         data[25- 1: 0],  1'b0}:          data[25:0];

endmodule  
module  float_add_sub_altbarrel_shift_olb
	( 
	data,
	distance,
	result) ;
	input   [25:0]  data;
	input   [4:0]  distance;
	output  [25:0]  result;

	wire	[25:0]	smux_w0;
	wire	[25:0]	smux_w1;
	wire	[25:0]	smux_w2;
	wire	[25:0]	smux_w3;

  assign result  = distance[4] ? {16'b0, smux_w3[25:16] } : smux_w3[25:0];
  assign smux_w3 = distance[3] ? { 8'b0, smux_w2[25: 8] } : smux_w2[25:0];
  assign smux_w2 = distance[2] ? { 4'b0, smux_w1[25: 4] } : smux_w1[25:0];
  assign smux_w1 = distance[1] ? { 2'b0, smux_w0[25: 2] } : smux_w0[25:0];
  assign smux_w0 = distance[0] ? { 1'b0,    data[25: 1] } :    data[25:0];

endmodule 

module  leading_zeroes_cnt
	( 
	data,
	q) ;
	input   [31:0]  data;
	output reg [4:0]  q;

always @(*) begin
  casez ({data})
    32'b1???_????_????_????_????_????_????_????:begin q <= 31; end
    32'b01??_????_????_????_????_????_????_????:begin q <= 30; end
    32'b001?_????_????_????_????_????_????_????:begin q <= 29; end
    32'b0001_????_????_????_????_????_????_????:begin q <= 28; end
    32'b0000_1???_????_????_????_????_????_????:begin q <= 27; end
    32'b0000_01??_????_????_????_????_????_????:begin q <= 26; end
    32'b0000_001?_????_????_????_????_????_????:begin q <= 25; end
    32'b0000_0001_????_????_????_????_????_????:begin q <= 24; end
    32'b0000_0000_1???_????_????_????_????_????:begin q <= 23; end
    32'b0000_0000_01??_????_????_????_????_????:begin q <= 22; end
    32'b0000_0000_001?_????_????_????_????_????:begin q <= 21; end
    32'b0000_0000_0001_????_????_????_????_????:begin q <= 20; end
    32'b0000_0000_0000_1???_????_????_????_????:begin q <= 19; end
    32'b0000_0000_0000_01??_????_????_????_????:begin q <= 18; end
    32'b0000_0000_0000_001?_????_????_????_????:begin q <= 17; end
    32'b0000_0000_0000_0001_????_????_????_????:begin q <= 16; end
    32'b0000_0000_0000_0000_1???_????_????_????:begin q <= 15; end
    32'b0000_0000_0000_0000_01??_????_????_????:begin q <= 14; end
    32'b0000_0000_0000_0000_001?_????_????_????:begin q <= 13; end
    32'b0000_0000_0000_0000_0001_????_????_????:begin q <= 12; end
    32'b0000_0000_0000_0000_0000_1???_????_????:begin q <= 11; end
    32'b0000_0000_0000_0000_0000_01??_????_????:begin q <= 10; end
    32'b0000_0000_0000_0000_0000_001?_????_????:begin q <=  9; end
    32'b0000_0000_0000_0000_0000_0001_????_????:begin q <=  8; end
    32'b0000_0000_0000_0000_0000_0000_1???_????:begin q <=  7; end
    32'b0000_0000_0000_0000_0000_0000_01??_????:begin q <=  6; end
    32'b0000_0000_0000_0000_0000_0000_001?_????:begin q <=  5; end
    32'b0000_0000_0000_0000_0000_0000_0001_????:begin q <=  4; end
    32'b0000_0000_0000_0000_0000_0000_0000_1???:begin q <=  3; end
    32'b0000_0000_0000_0000_0000_0000_0000_01??:begin q <=  2; end
    32'b0000_0000_0000_0000_0000_0000_0000_001?:begin q <=  1; end
    32'b0000_0000_0000_0000_0000_0000_0000_0001:begin q <=  0; end
    default:                                    begin q <=  0; end
  endcase
end

endmodule

module  trailing_zeros_cnt
	( 
	data,
	q) ;
	input   [31:0]  data;
	output reg [4:0]  q;

always @(*) begin
  casez ({data})
    32'b????_????_????_????_????_????_????_???1:begin q <=  0; end
    32'b????_????_????_????_????_????_????_??10:begin q <=  1; end
    32'b????_????_????_????_????_????_????_?100:begin q <=  2; end
    32'b????_????_????_????_????_????_????_1000:begin q <=  3; end
    32'b????_????_????_????_????_????_???1_0000:begin q <=  4; end
    32'b????_????_????_????_????_????_??10_0000:begin q <=  5; end
    32'b????_????_????_????_????_????_?100_0000:begin q <=  6; end
    32'b????_????_????_????_????_????_1000_0000:begin q <=  7; end
    32'b????_????_????_????_????_???1_0000_0000:begin q <=  8; end
    32'b????_????_????_????_????_??10_0000_0000:begin q <=  9; end
    32'b????_????_????_????_????_?100_0000_0000:begin q <= 10; end
    32'b????_????_????_????_????_1000_0000_0000:begin q <= 11; end
    32'b????_????_????_????_???1_0000_0000_0000:begin q <= 12; end
    32'b????_????_????_????_??10_0000_0000_0000:begin q <= 13; end
    32'b????_????_????_????_?100_0000_0000_0000:begin q <= 14; end
    32'b????_????_????_????_1000_0000_0000_0000:begin q <= 15; end
    32'b????_????_????_???1_0000_0000_0000_0000:begin q <= 16; end
    32'b????_????_????_??10_0000_0000_0000_0000:begin q <= 17; end
    32'b????_????_????_?100_0000_0000_0000_0000:begin q <= 18; end
    32'b????_????_????_1000_0000_0000_0000_0000:begin q <= 19; end
    32'b????_????_???1_0000_0000_0000_0000_0000:begin q <= 20; end
    32'b????_????_??10_0000_0000_0000_0000_0000:begin q <= 21; end
    32'b????_????_?100_0000_0000_0000_0000_0000:begin q <= 22; end
    32'b????_????_1000_0000_0000_0000_0000_0000:begin q <= 23; end
    32'b????_???1_0000_0000_0000_0000_0000_0000:begin q <= 24; end
    32'b????_??10_0000_0000_0000_0000_0000_0000:begin q <= 25; end
    32'b????_?100_0000_0000_0000_0000_0000_0000:begin q <= 26; end
    32'b????_1000_0000_0000_0000_0000_0000_0000:begin q <= 27; end
    32'b???1_0000_0000_0000_0000_0000_0000_0000:begin q <= 28; end
    32'b??10_0000_0000_0000_0000_0000_0000_0000:begin q <= 29; end
    32'b?100_0000_0000_0000_0000_0000_0000_0000:begin q <= 30; end
    32'b1000_0000_0000_0000_0000_0000_0000_0000:begin q <= 31; end
    default:                                    begin q <= 31; end
  endcase
end

endmodule

module float_add_sub (
	add_sub,
	clock,
	dataa,
	datab,
	result);

	input	  add_sub;
	input	  clock;
	input	[31:0]  dataa;
	input	[31:0]  datab;
	output	[31:0]  result;


//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

	wire  exp_a_not_zero_w = |dataa[30:23];
	wire  exp_b_not_zero_w = |datab[30:23];
	wire  exp_a_all_one_w = &dataa[30:23];
	wire  exp_b_all_one_w = &datab[30:23];
	wire  man_a_not_zero_w = |dataa[22:0];
	wire  man_b_not_zero_w = |datab[22:0];
	wire  input_dataa_infinite_w = (exp_a_all_one_w & (~ man_a_not_zero_w));
	wire  input_datab_infinite_w = (exp_b_all_one_w & (~ man_b_not_zero_w));
	wire  input_dataa_denormal_w = ((~ exp_a_not_zero_w) & man_a_not_zero_w);
	wire  input_datab_denormal_w = ((~ exp_b_not_zero_w) & man_b_not_zero_w);
	wire  input_dataa_zero_w = ((~ exp_a_not_zero_w) & (~ man_a_not_zero_w));
	wire  input_datab_zero_w = ((~ exp_b_not_zero_w) & (~ man_b_not_zero_w));
	wire  input_dataa_nan_w = (exp_a_all_one_w & man_a_not_zero_w);
	wire  input_datab_nan_w = (exp_b_all_one_w & man_b_not_zero_w);
	wire  [25:0]  aligned_dataa_man_w = {(((~ input_dataa_infinite_w) & (~ input_dataa_denormal_w)) & (~ input_dataa_zero_w)), ({23{(~ input_dataa_denormal_w)}} & dataa[22:0]), {2{1'b0}}};
	wire  [25:0]  aligned_datab_man_w = {(((~ input_datab_infinite_w) & (~ input_datab_denormal_w)) & (~ input_datab_zero_w)), ({23{(~ input_datab_denormal_w)}} & datab[22:0]), {2{1'b0}}};


	wire aligned_dataa_sign_w = dataa[31];
	wire [8:0] aligned_datab_exp_w = {1'b0, ({8{(~ input_datab_denormal_w)}} & datab[30:23])};
	wire aligned_datab_sign_w = datab[31];
	wire [8:0] aligned_dataa_exp_w = {1'b0, ({8{(~ input_dataa_denormal_w)}} & dataa[30:23])};
  wire [8:0] exp_amb_w = aligned_dataa_exp_w - aligned_datab_exp_w;
  wire [8:0] exp_bma_w = aligned_datab_exp_w - aligned_dataa_exp_w;
	wire  input_is_nan_dffe1_wi = (input_dataa_nan_w | input_datab_nan_w);
	wire  infinite_output_sign_dffe1_wi = input_datab_infinite_w ? (~ (aligned_datab_sign_w ^ add_sub)) : aligned_dataa_sign_w;
	wire  both_inputs_are_infinite_dffe1_wi = (input_dataa_infinite_w & input_datab_infinite_w);
	wire  input_is_infinite_dffe1_wi = (input_dataa_infinite_w | input_datab_infinite_w);
	wire  exp_amb_mux_w = exp_amb_w[8];
	wire  [23:0]  man_smaller_w = exp_amb_mux_w ? aligned_dataa_man_w[25:2] : aligned_datab_man_w[25:2];

	wire  [4:0]  exp_diff_abs_max_w = {5{1'b1}};
	wire  [7:0]  exp_diff_abs_w = exp_amb_mux_w ? exp_bma_w[7:0] : exp_amb_w[7:0];
	wire  exp_diff_abs_exceed_max_w = |exp_diff_abs_w[7:5];
	wire  [4:0]  rshift_distance_w = exp_diff_abs_exceed_max_w ? exp_diff_abs_max_w : exp_diff_abs_w[4:0];

	wire  [25:0]   wire_rbarrel_shift_result;
	float_add_sub_altbarrel_shift_olb   rbarrel_shift
	( 
	.data({man_smaller_w, {2{1'b0}}}),
	.distance(rshift_distance_w),
	.result(wire_rbarrel_shift_result));

	wire  [4:0]   wire_trailing_zeros_cnt_q;
	trailing_zeros_cnt   trailing_zeros_cnt_inst
	( 
	.data({{9{1'b1}}, man_smaller_w[22:0]}),
	.q(wire_trailing_zeros_cnt_q)
  );

	wire  [5:0]   wire_add_sub3_result = {1'b0, rshift_distance_w} - {1'b0, wire_trailing_zeros_cnt_q};

	wire  [5:0]  trailing_zeros_limit_w = 6'b000010;
	wire  wire_trailing_zeros_limit_comparator_agb = $signed(wire_add_sub3_result) > $signed(trailing_zeros_limit_w);

	wire  [7:0]  data_exp_dffe1_wi = exp_amb_mux_w ? aligned_datab_exp_w[7:0] : aligned_dataa_exp_w[7:0];
	wire  [25:0]  dataa_man_dffe1_wi = exp_amb_mux_w ? wire_rbarrel_shift_result : aligned_dataa_man_w;
	wire  [25:0]  datab_man_dffe1_wi = exp_amb_mux_w ? aligned_datab_man_w : wire_rbarrel_shift_result;
  
	reg	[25:0]	dataa_man_dffe1;
	reg	dataa_sign_dffe1;
	reg	[25:0]	datab_man_dffe1;
	reg	datab_sign_dffe1;
	reg	[7:0]	data_exp_dffe1;
	reg	both_inputs_are_infinite_dffe1;
	reg	add_sub_dffe1;
	reg	infinite_output_sign_dffe1;
	reg	input_is_infinite_dffe1;
	reg	input_is_nan_dffe1;
	reg	sticky_bit_dffe1;
	always @ (posedge clock) begin
		dataa_sign_dffe1 <= aligned_dataa_sign_w;
		datab_sign_dffe1 <= aligned_datab_sign_w;
    input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
    infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
    both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
    input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
    data_exp_dffe1 <= data_exp_dffe1_wi;
    dataa_man_dffe1 <= dataa_man_dffe1_wi;
    datab_man_dffe1 <= datab_man_dffe1_wi;
    add_sub_dffe1 <= add_sub;
    sticky_bit_dffe1 <= wire_trailing_zeros_limit_comparator_agb;
  end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------


	reg add_sub_w2;
  always @ (*)begin
    case({dataa_sign_dffe1, datab_sign_dffe1})
      0: begin add_sub_w2 <= add_sub_dffe1; end
      1: begin add_sub_w2 <= ~add_sub_dffe1; end
      2: begin add_sub_w2 <= ~add_sub_dffe1; end
      3: begin add_sub_w2 <= add_sub_dffe1; end
    endcase
  end

	wire  zero_man_sign_dffe2_wi = (dataa_sign_dffe1 & add_sub_w2);
	wire  infinity_magnitude_sub_dffe2_wi = ((~ add_sub_w2) & both_inputs_are_infinite_dffe1);

	wire [1:0] pos_sign_bit_ext = {2{1'b0}};
	wire [27:0] man_2comp_res_dataa_w = {pos_sign_bit_ext, datab_man_dffe1};
	wire [27:0] man_2comp_res_datab_w = {pos_sign_bit_ext, dataa_man_dffe1};
	wire [27:0] man_add_sub_dataa_w = {pos_sign_bit_ext, dataa_man_dffe1};
	wire [27:0] man_add_sub_datab_w = {pos_sign_bit_ext, datab_man_dffe1};
	wire borrow_w = ((~ sticky_bit_dffe1) & (~ add_sub_w2));

	reg  [27:0] wire_add_sub4_result;
	reg  [27:0] wire_add_sub5_result;
	reg	[7:0]	exp_res_dffe2;
	reg	infinite_output_sign_dffe2;
	reg	infinity_magnitude_sub_dffe2;
	reg	input_is_infinite_dffe2;
	reg	input_is_nan_dffe2;
	reg	need_complement_dffe2;
	reg	zero_man_sign_dffe2;
	reg	sticky_bit_dffe2;
	always @ (posedge clock)begin
		need_complement_dffe2 <= dataa_sign_dffe1;
    input_is_nan_dffe2 <= input_is_nan_dffe1;
    infinite_output_sign_dffe2 <= infinite_output_sign_dffe1;
    input_is_infinite_dffe2 <= input_is_infinite_dffe1;
    exp_res_dffe2 <= data_exp_dffe1;
    sticky_bit_dffe2 <= sticky_bit_dffe1;
    infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
    zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
    wire_add_sub4_result = add_sub_w2 == 0 ? (man_add_sub_dataa_w - man_add_sub_datab_w + borrow_w) : (man_add_sub_dataa_w + man_add_sub_datab_w + borrow_w);
    wire_add_sub5_result = add_sub_w2 == 0 ? (man_2comp_res_dataa_w - man_2comp_res_datab_w + borrow_w) : (man_2comp_res_dataa_w + man_2comp_res_datab_w + borrow_w);
  end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
	wire  [1:0]  exp_adjust_by_add1 = 2'b01;
	wire  [1:0]  exp_adjust_by_add2 = 2'b10;

	wire  [27:0]  man_add_sub_res_mag_w2 = wire_add_sub4_result[27] ? wire_add_sub5_result : wire_add_sub4_result;
	wire  man_add_sub_res_sign_w2 = need_complement_dffe2 ? (~ wire_add_sub4_result[27]) : wire_add_sub4_result[27];
	wire  [1:0]  exp_adj_dffe21_wi = man_add_sub_res_mag_w2[26] ? exp_adjust_by_add2 : exp_adjust_by_add1;
	wire  [25:0]  man_res_mag_w2 = man_add_sub_res_mag_w2[26] ? man_add_sub_res_mag_w2[26:1] : man_add_sub_res_mag_w2[25:0];

	reg	[1:0]	exp_adj_dffe21;
	reg	[7:0]	exp_res_dffe21;
	reg	infinite_output_sign_dffe21;
	reg	infinity_magnitude_sub_dffe21;
	reg	input_is_infinite_dffe21;
	reg	input_is_nan_dffe21;
	reg	[25:0]	man_add_sub_res_mag_dffe21;
	reg	man_add_sub_res_sign_dffe21;
	reg	round_bit_dffe21;
	reg	sticky_bit_dffe21;
	reg	zero_man_sign_dffe21;
	always @ (posedge clock)begin
    input_is_nan_dffe21 <= input_is_nan_dffe2;
    infinite_output_sign_dffe21 <= infinite_output_sign_dffe2;
    input_is_infinite_dffe21 <= input_is_infinite_dffe2;
    exp_res_dffe21 <= exp_res_dffe2;
    exp_adj_dffe21 <= exp_adj_dffe21_wi;
    man_add_sub_res_mag_dffe21 <= man_res_mag_w2;
    case(man_add_sub_res_mag_w2[26:25])
      0: begin round_bit_dffe21 <= man_add_sub_res_mag_w2[0]; sticky_bit_dffe21 <= sticky_bit_dffe2; end
      1: begin round_bit_dffe21 <= man_add_sub_res_mag_w2[1]; sticky_bit_dffe21 <= (sticky_bit_dffe2 | man_add_sub_res_mag_w2[0]); end
      2: begin round_bit_dffe21 <= man_add_sub_res_mag_w2[2]; sticky_bit_dffe21 <= ((sticky_bit_dffe2 | man_add_sub_res_mag_w2[0]) | man_add_sub_res_mag_w2[1]); end
      3: begin round_bit_dffe21 <= man_add_sub_res_mag_w2[2]; sticky_bit_dffe21 <= ((sticky_bit_dffe2 | man_add_sub_res_mag_w2[0]) | man_add_sub_res_mag_w2[1]); end
    endcase

    infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe2;
    zero_man_sign_dffe21 <= zero_man_sign_dffe2;
    man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_w2;
  end

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
	wire  [3:0]  priority_encoder_1pads_w = {4{1'b1}};
	wire  [6:0]  exp_adj_0pads = {7{1'b0}};
	wire  [8:0]  exp_value = {1'b0, exp_res_dffe21};
	wire  [4:0]   wire_leading_zeroes_cnt_q;
	leading_zeroes_cnt   leading_zeroes_cnt_inst
	( 
	.data({man_add_sub_res_mag_dffe21[25:1], 1'b1, {6{1'b0}}}),
	.q(wire_leading_zeroes_cnt_q)
  );
	wire  [4:0]  man_leading_zeros_dffe31_wi = (~ wire_leading_zeroes_cnt_q);
	wire  [8:0]  exp_adjustment_add_sub_dataa_w = {priority_encoder_1pads_w, wire_leading_zeroes_cnt_q};
	wire  [8:0]  exp_adjustment_add_sub_datab_w = {exp_adj_0pads, exp_adj_dffe21};

	wire  man_res_not_zero_w2 = |man_add_sub_res_mag_dffe21[25:1];
	wire  sign_dffe31_wi = man_res_not_zero_w2 ? man_add_sub_res_sign_dffe21 : zero_man_sign_dffe21;
  
	reg  [8:0]   wire_add_sub7_result;
	reg	infinite_output_sign_dffe31;
	reg	[4:0]	man_leading_zeros_dffe31;
	reg	man_res_is_not_zero_dffe31;
	reg	round_bit_dffe31;
	reg	input_is_nan_dffe31;
	reg	input_is_infinite_dffe31;
	reg	infinity_magnitude_sub_dffe31;
	reg	[25:0]	man_dffe31;
	reg	sign_dffe31;
	reg	sticky_bit_dffe31;
	always @ (posedge clock)begin
		input_is_nan_dffe31 <= input_is_nan_dffe21;
    infinite_output_sign_dffe31 <= infinite_output_sign_dffe21;
    input_is_infinite_dffe31 <= input_is_infinite_dffe21;
    sticky_bit_dffe31 <= sticky_bit_dffe21;
    man_dffe31 <= man_add_sub_res_mag_dffe21;
    man_res_is_not_zero_dffe31 <= man_res_not_zero_w2;
    sign_dffe31 <= sign_dffe31_wi;
    round_bit_dffe31 <= round_bit_dffe21;
    infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe21;
    man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
    wire_add_sub7_result = exp_value + exp_adjustment_add_sub_dataa_w + exp_adjustment_add_sub_datab_w;
  end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
	wire  exp_res_not_zero_w = |wire_add_sub7_result[8:0];
	wire  denormal_result_w = ((~ exp_res_not_zero_w) | wire_add_sub7_result[8]);
	wire  [7:0]  exp_res_dffe3_wi = ({8{(~ denormal_result_w)}} & wire_add_sub7_result[7:0]);
	wire  exp_res_max_w = &wire_add_sub7_result[7:0];
	wire  infinite_res_dffe3_wi = (exp_res_max_w & (~ wire_add_sub7_result[8]));

	wire aclr = 1'b0;
	wire clk_en = 1'b1;
	wire  [25:0]   wire_lbarrel_shift_result;
	float_add_sub_altbarrel_shift_35e   lbarrel_shift
	( 
	.aclr(aclr),
	.clk_en(clk_en),
	.clock(clock),
	.data(man_dffe31),
	.distance(man_leading_zeros_dffe31),
	.result(wire_lbarrel_shift_result));


	reg	man_res_is_not_zero_dffe3;
	reg	input_is_nan_dffe3;
	reg	[7:0]	exp_res_dffe3;
	reg	infinite_res_dffe3;
	reg	input_is_infinite_dffe3;
	reg	infinity_magnitude_sub_dffe3;
	reg	infinite_output_sign_dffe3;
	reg	denormal_res_dffe3;
	reg	round_bit_dffe3;
	reg	sign_res_dffe3;
	reg	sticky_bit_dffe3;
	always @ (posedge clock)begin
    input_is_nan_dffe3 <= input_is_nan_dffe31;
    infinite_output_sign_dffe3 <= infinite_output_sign_dffe31;
    input_is_infinite_dffe3 <= input_is_infinite_dffe31;
    sticky_bit_dffe3 <= sticky_bit_dffe31;
    man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe31;
    sign_res_dffe3 <= sign_dffe31;
    round_bit_dffe3 <= round_bit_dffe31;
    infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe31;
    infinite_res_dffe3 <= infinite_res_dffe3_wi;
    exp_res_dffe3 <= exp_res_dffe3_wi;
    denormal_res_dffe3 <= denormal_result_w;
    //wire_lbarrel_shift_result  ????????
  end

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
	wire  [23:0] man_res_w3 = wire_lbarrel_shift_result[25:2];
	wire  man_rounding_add_value_w = (round_bit_dffe3 & (sticky_bit_dffe3 | man_res_w3[0]));
	wire  [25:0] wire_add_sub8_result = {{2{1'b0}}, man_res_w3} + {{25{1'b0}}, man_rounding_add_value_w};

	wire  [8:0] exp_res_rounding_adder_dataa_w = {1'b0, exp_res_dffe3};
	wire  [8:0] exp_rounding_adjustment_w = {{8{1'b0}}, wire_add_sub8_result[24]};
	wire  [8:0] wire_add_sub9_result = exp_res_rounding_adder_dataa_w + exp_rounding_adjustment_w;

	wire  exp_rounded_res_max_w = &wire_add_sub9_result[7:0];
	wire  [22:0] man_rounded_res_w = wire_add_sub8_result[24] ? wire_add_sub8_result[23:1] : wire_add_sub8_result[22:0];


	reg	denormal_res_dffe4;
	reg	[7:0]	exp_res_dffe4;
	reg	infinite_output_sign_dffe4;
	reg	infinite_res_dffe4;
	reg	infinity_magnitude_sub_dffe4;
	reg	input_is_infinite_dffe4;
	reg	input_is_nan_dffe4;
	reg	[22:0]	man_res_dffe4;
	reg	man_res_is_not_zero_dffe4;
	reg	rounded_res_infinity_dffe4;
	reg	sign_res_dffe4;
	//always @ ( posedge clock) begin
	always @ ( *) begin
    denormal_res_dffe4 <= denormal_res_dffe3;
    man_res_dffe4 <= man_rounded_res_w;
    exp_res_dffe4 <= wire_add_sub9_result[7:0];
    man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe3;
    sign_res_dffe4 <= sign_res_dffe3;
    infinite_output_sign_dffe4 <= infinite_output_sign_dffe3;
    infinite_res_dffe4 <= infinite_res_dffe3;
    rounded_res_infinity_dffe4 <= exp_rounded_res_max_w;
    input_is_infinite_dffe4 <= input_is_infinite_dffe3;
		infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe3;
    input_is_nan_dffe4 <= input_is_nan_dffe3;
  end

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

	wire  [22:0]  man_nan_w = 23'b10000000000000000000000;
	wire  [22:0] man_all_zeros_w = {23{1'b0}};
	wire  force_infinity_w = ((input_is_infinite_dffe4 | rounded_res_infinity_dffe4) | infinite_res_dffe4);
	wire  force_nan_w = (infinity_magnitude_sub_dffe4 | input_is_nan_dffe4);
	wire  force_zero_w = (~ man_res_is_not_zero_dffe4);
	wire  denormal_flag_w = ((((~ force_nan_w) & (~ force_infinity_w)) & (~ force_zero_w)) & denormal_res_dffe4);
	wire  [7:0]  exp_all_ones_w = {8{1'b1}};
	wire  [7:0]  exp_all_zeros_w = {8{1'b0}};
	wire  sign_out_dffe5_wi = force_infinity_w ? infinite_output_sign_dffe4 : sign_res_dffe4;
	wire  [7:0]  exp_out_dffe5_wi = force_infinity_w ? exp_all_ones_w : ((force_zero_w | denormal_flag_w) ? exp_all_zeros_w : exp_res_dffe4);
	wire  [22:0]  man_out_dffe5_wi = force_infinity_w ? man_all_zeros_w : ((force_zero_w | denormal_flag_w) ? man_all_zeros_w : man_res_dffe4);
	
  assign result = force_nan_w ? {1'b0, exp_all_ones_w, man_nan_w} : {sign_out_dffe5_wi, exp_out_dffe5_wi, man_out_dffe5_wi};
endmodule 

